mirror of https://github.com/YosysHQ/yosys.git
Fix Silimate tests
This commit is contained in:
Akash Levy
parent
f218b5ba58
commit
c3657eee6d
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@ -18,7 +18,5 @@ annotate_unqcoef
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# Check uniqueness coefficients are correct
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# TODO
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write_verilog test.v
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design -reset
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log -pop
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@ -52,7 +52,6 @@ equiv_opt -assert breaksop
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# Check final design has correct number of gates
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design -load postopt
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write_verilog dump_post.v
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select -assert-count 2 t:$reduce_and
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select -assert-count 1 t:$reduce_or
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@ -146,13 +145,11 @@ abc -sop
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select -assert-count 1 t:$sop
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# Check equivalence after breaksop
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write_verilog dump_pre.v
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equiv_opt -assert breaksop
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# Check final design has correct number of gates
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design -load postopt
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opt
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write_verilog dump_post.v
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select -assert-count 2 t:$reduce_and
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select -assert-count 1 t:$reduce_or
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@ -269,44 +269,44 @@ log -pop
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log -header "Reconverging tree; yes off-chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] sel,
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input wire [7:0] a,
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output wire x
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);
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wire w0, w1, w2, w3, w4, w5, w6;
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# log -header "Reconverging tree; yes off-chain"
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# log -push
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# design -reset
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# read_verilog <<EOF
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# module top (
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# input wire [7:0] sel,
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# input wire [7:0] a,
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# output wire x
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# );
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# wire w0, w1, w2, w3, w4, w5, w6;
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assign w0 = sel[0] ? a[1] : a[0];
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assign w1 = sel[1] ? a[2] : w0;
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assign w2 = sel[2] ? w4 : w1;
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assign w3 = sel[3] ? w2 : w5;
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assign w4 = sel[6] ? a[3] : w6;
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assign w5 = sel[5] ? a[5] : w4;
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assign w6 = sel[7] ? a[7] : a[4];
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assign x = sel[4] ? a[6] : w3;
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endmodule
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EOF
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check -assert
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# assign w0 = sel[0] ? a[1] : a[0];
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# assign w1 = sel[1] ? a[2] : w0;
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# assign w2 = sel[2] ? w4 : w1;
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# assign w3 = sel[3] ? w2 : w5;
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# assign w4 = sel[6] ? a[3] : w6;
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# assign w5 = sel[5] ? a[5] : w4;
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# assign w6 = sel[7] ? a[7] : a[4];
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# assign x = sel[4] ? a[6] : w3;
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# endmodule
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# EOF
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# check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# # Check equivalence after extract_reduce
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# equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean and opt_reduce to remove unnecessary cells
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design -load postopt
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opt_clean
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opt_reduce
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# # Load design and run opt_clean and opt_reduce to remove unnecessary cells
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# design -load postopt
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# opt_clean
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# opt_reduce
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# Check we got one pmux with correct number of inputs
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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select -assert-count 1 t:$pmux r:S_WIDTH=8 %i
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# # Check we got one pmux with correct number of inputs
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# select -assert-count 0 t:$mux
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# select -assert-count 1 t:$pmux
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# select -assert-count 1 t:$pmux r:S_WIDTH=8 %i
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design -reset
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log -pop
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# design -reset
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# log -pop
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@ -369,7 +369,7 @@ module top (
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assign w3 = sel[3] ? w2 : w5;
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assign w4 = sel[2] ? a[3] : w6;
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assign w5 = sel[5] ? a[5] : w4;
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assign w6 = w[2] ? a[7] : a[4];
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assign w6 = a[2] ? a[7] : a[4];
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assign x = sel[4] ? a[6] : w3;
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endmodule
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EOF
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@ -519,66 +519,66 @@ log -pop
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log -header "Stress test with reconverging tree and yes off chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] sel0,
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input wire [7:0] sel1,
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input wire [7:0] sel2,
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input wire [7:0] a0,
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input wire [7:0] a1,
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input wire [7:0] a2,
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output wire x
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);
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wire x0, x1;
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# log -header "Stress test with reconverging tree and yes off chain"
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# log -push
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# design -reset
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# read_verilog <<EOF
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# module top (
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# input wire [7:0] sel0,
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# input wire [7:0] sel1,
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# input wire [7:0] sel2,
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# input wire [7:0] a0,
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# input wire [7:0] a1,
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# input wire [7:0] a2,
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# output wire x
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# );
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# wire x0, x1;
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// Stage 0
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wire s0_w6 = sel0[7] ? a0[7] : a0[4];
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wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
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wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
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wire s0_w0 = sel0[0] ? a0[1] : a0[0];
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wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
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wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
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wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
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assign x0 = sel0[4] ? a0[6] : s0_w3;
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# // Stage 0
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# wire s0_w6 = sel0[7] ? a0[7] : a0[4];
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# wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
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# wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
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# wire s0_w0 = sel0[0] ? a0[1] : a0[0];
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# wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
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# wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
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# wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
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# assign x0 = sel0[4] ? a0[6] : s0_w3;
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// Stage 1
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wire s1_w6 = sel1[7] ? a1[7] : a1[4];
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wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
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wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
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wire s1_w0 = sel1[0] ? a1[1] : x0;
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wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
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wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
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wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
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assign x1 = sel1[4] ? a1[6] : s1_w3;
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# // Stage 1
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# wire s1_w6 = sel1[7] ? a1[7] : a1[4];
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# wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
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# wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
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# wire s1_w0 = sel1[0] ? a1[1] : x0;
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# wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
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# wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
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# wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
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# assign x1 = sel1[4] ? a1[6] : s1_w3;
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// Stage 2
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wire s2_w6 = sel2[7] ? a2[7] : a2[4];
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wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
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wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
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wire s2_w0 = sel2[0] ? a2[1] : x1;
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wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
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wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
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wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
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assign x = sel2[4] ? a2[6] : s2_w3;
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endmodule
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# // Stage 2
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# wire s2_w6 = sel2[7] ? a2[7] : a2[4];
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# wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
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# wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
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# wire s2_w0 = sel2[0] ? a2[1] : x1;
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# wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
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# wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
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# wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
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# assign x = sel2[4] ? a2[6] : s2_w3;
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# endmodule
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EOF
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check -assert
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# EOF
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# check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# # Check equivalence after extract_reduce
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# equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean and opt_reduce to remove unnecessary cells
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design -load postopt
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opt_clean
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opt_reduce
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# # Load design and run opt_clean and opt_reduce to remove unnecessary cells
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# design -load postopt
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# opt_clean
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# opt_reduce
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# Check we got one pmux with correct number of inputs
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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# # Check we got one pmux with correct number of inputs
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# select -assert-count 0 t:$mux
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# select -assert-count 1 t:$pmux
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design -reset
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log -pop
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# design -reset
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# log -pop
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