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Added output args to synth_ice40

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Clifford Wolf
2015-05-26 17:08:53 +02:00
parent 08a4af3cde
commit c329233f0d
2 changed files with 37 additions and 2 deletions
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techlibs/xilinx/synth_xilinx.cc
+2 -2
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@@ -110,8 +110,8 @@ struct SynthXilinxPass : public Pass {
log(" stat\n");
log(" check -noinit\n");
log("\n");
log(" edif:\n");
log(" write_edif synth.edif\n");
log(" edif: (only if -edif)\n");
log(" write_edif <file-name>\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)