mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-08-22 14:17:27 +02:00
Docs: Fix word_logic.rst
It somehow got lost in the rebase.
This commit is contained in:
@@ -23,6 +23,7 @@ Simulation models for the RTL cells can be found in the file
|
||||
/cell/word_mem
|
||||
/cell/word_fsm
|
||||
/cell/word_arith
|
||||
/cell/word_logic
|
||||
/cell/word_spec
|
||||
/cell/word_formal
|
||||
/cell/word_debug
|
||||
|
||||
Reference in New Issue
Block a user