mirror of https://github.com/YosysHQ/yosys.git
added deeper cases for gates
This commit is contained in:
williamzhu17
parent
2f9e6e08f0
commit
bc2d9d1f33
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@ -95,7 +95,7 @@ log -pop
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log -header "No off-chain"
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log -header "No off-chain for AND"
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log -push
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design -reset
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read_verilog <<EOF
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@ -176,6 +176,85 @@ select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
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design -reset
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log -pop
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log -header "No off-chain with branches for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
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assign x = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that both gates are 6 bits wide
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select -assert-none t:$reduce_and r:A_WIDTH!=6 %i
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design -reset
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log -pop
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log -header "Allow off-chain with branches for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
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assign x = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that only one gate has a width of 11 and one gate has a width of 6
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select -assert-count 1 t:$reduce_and r:A_WIDTH=11 %i
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select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
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design -reset
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log -pop
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###################################################################
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# Extract Reduce OR Gates Tests
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###################################################################
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@ -354,6 +433,85 @@ select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
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design -reset
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log -pop
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log -header "No off-chain with branches for OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
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assign x = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_or
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# Check that both gates are 6 bits wide
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select -assert-none t:$reduce_or r:A_WIDTH!=6 %i
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design -reset
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log -pop
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log -header "Allow off-chain with branches for OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
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assign x = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_or
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# Check that only one gate has a width of 11 and one gate has a width of 6
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select -assert-count 1 t:$reduce_or r:A_WIDTH=11 %i
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select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
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design -reset
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log -pop
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###################################################################
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# Extract Reduce XOR Gates Tests
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###################################################################
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@ -535,6 +693,83 @@ log -pop
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log -header "No off-chain with branches for XOR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
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assign x = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$xor
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select -assert-count 2 t:$reduce_xor
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# Check that both gates are 6 bits wide
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select -assert-none t:$reduce_xor r:A_WIDTH!=6 %i
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design -reset
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log -pop
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log -header "Allow off-chain with branches for XOR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
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assign x = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$xor
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select -assert-count 2 t:$reduce_xor
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# Check that only one gate has a width of 11 and one gate has a width of 6
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select -assert-count 1 t:$reduce_xor r:A_WIDTH=11 %i
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select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
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design -reset
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log -pop
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###################################################################
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# Extract PMUX from MUX Chains Tests
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###################################################################
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