tests: Add bug3515

tests/various/bug3515.v

@@ -0,0 +1,26 @@
+// Triple AND GATE
+module mod_74x08_3 (
+    input A_1,
+    input B_1,
+    input A_2,
+    input B_2,
+    input A_3,
+    input B_3,
+    output Y_1,
+    output Y_2,
+    output Y_3);
+
+assign Y_1 = A_1 & B_1;
+assign Y_2 = A_2 & B_2;
+assign Y_3 = A_3 & B_3;
+
+endmodule
+
+// OR GATE
+module mod_74x32_1 (
+    input A_1,
+    input B_1,
+    output Y_1);
+
+assign Y_1 = A_1 | B_1;
+endmodule

tests/various/bug3515.ys

@@ -0,0 +1,21 @@
+read_verilog << EOF
+module mod_and_or (
+    input a,
+    input b,
+    input c,
+    input d,
+    output reg y
+);
+
+always @(a,b,c,d) begin
+    y <= (a&b)|(c&d);
+end
+endmodule
+EOF
+hierarchy -top mod_and_or
+proc
+opt
+techmap -map ./bug3515.v
+proc
+extract -map ./bug3515.v -verbose
+proc