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https://github.com/YosysHQ/yosys.git
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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@@ -58,7 +58,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
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{
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log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
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RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
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for (auto &conn : cell->connections_) {
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for (auto &conn : cell->connections()) {
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RTLIL::SigSpec sig = sigmap(conn.second);
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port_sigs.push_back(sig);
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}
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@@ -80,8 +80,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
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for (RTLIL::Wire *wire : ports) {
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log_assert(wire != NULL);
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RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
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if (cell->connections_.count(wire->name) > 0) {
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sig = sigmap(cell->connections_.at(wire->name));
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if (cell->connections().count(wire->name) > 0) {
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sig = sigmap(cell->connections().at(wire->name));
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sig.extend(wire->width, false);
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}
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port_sigs.push_back(sig);
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@@ -98,7 +98,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
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fprintf(f, " %s\n", RTLIL::id2cstr(cell->type));
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}
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for (auto &conn : module->connections_)
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for (auto &conn : module->connections())
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for (int i = 0; i < conn.first.size(); i++) {
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fprintf(f, "V%d", conn_counter++);
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print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);
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