Add logic param and integer bad syntax tests

Signed-off-by: Kamil Rakoczy <[email protected]>
2026-08-22 06:07:26 +02:00 · 2020-07-06 09:18:48 +02:00
parent 7e83a51fc9
commit b422f2e4d0
3 changed files with 21 additions and 0 deletions
@@ -0,0 +1,6 @@
+logger -expect error "syntax error, unexpected TOK_REAL" 1
+read_verilog -sv <<EOT
+module test_integer_real();
+parameter integer real a = 0;
+endmodule
+EOT