mirror of https://github.com/YosysHQ/yosys.git
Don't raise DZ when left is inf
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@ -1 +1 @@
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Subproject commit 1452b0b39c40c1a22dcbb0cc5b22ab628247ee5b
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Subproject commit f5eccd09323fba1a7ee78df2e7bb43dc5509dfe5
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@ -228,9 +228,8 @@ module edges();
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`ifdef DIV
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`ifdef DIV
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assume (c_zero);
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assume (c_zero);
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// a = finite, b = 0
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// div/zero when a = finite, b = 0
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if ((a_norm || a_subnorm) && b_unsigned == '0)
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assert (!DZ || ((a_norm || a_subnorm) && b_unsigned == '0));
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assert (DZ);
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// 0/0 or inf/inf
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// 0/0 or inf/inf
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if ((a_zero && b_zero) || (a_inf && b_inf))
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if ((a_zero && b_zero) || (a_inf && b_inf))
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assert (NV);
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assert (NV);
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