mirror of https://github.com/YosysHQ/yosys.git
Actually fix wreduce
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dfc8607a77
commit
b2f2d6d6e3
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@ -142,6 +142,7 @@ struct WreduceWorker
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mi.notify_connect(cell, ID::A, sig_a, new_sig_a);
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mi.notify_connect(cell, ID::A, sig_a, new_sig_a);
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mi.notify_connect(cell, ID::B, sig_b, new_sig_b);
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mi.notify_connect(cell, ID::B, sig_b, new_sig_b);
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mi.notify_connect(cell, ID::Y, sig_y, new_sig_y);
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mi.notify_connect(cell, ID::Y, sig_y, new_sig_y);
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mi.sigmap.set(module);
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module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
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module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
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mi.notify_connect(module, SigSig(sig_y.extract(n_kept, n_removed), sig_removed));
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mi.notify_connect(module, SigSig(sig_y.extract(n_kept, n_removed), sig_removed));
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@ -244,6 +245,7 @@ struct WreduceWorker
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cell->fixup_parameters();
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cell->fixup_parameters();
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mi.notify_connect(cell, ID::D, sig_d_orig, sig_d);
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mi.notify_connect(cell, ID::D, sig_d_orig, sig_d);
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mi.notify_connect(cell, ID::Q, sig_q_orig, sig_q);
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mi.notify_connect(cell, ID::Q, sig_q_orig, sig_q);
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mi.sigmap.set(module);
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}
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}
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void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something)
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void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something)
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@ -277,6 +279,7 @@ struct WreduceWorker
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cell->setPort(stringf("\\%c", port), sig);
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cell->setPort(stringf("\\%c", port), sig);
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cell->fixup_parameters();
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cell->fixup_parameters();
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mi.notify_connect(cell, stringf("\\%c", port), sig_orig, sig);
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mi.notify_connect(cell, stringf("\\%c", port), sig_orig, sig);
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mi.sigmap.set(module);
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did_something = true;
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did_something = true;
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}
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}
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}
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}
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@ -464,6 +467,7 @@ struct WreduceWorker
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cell->setPort(ID::Y, sig);
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cell->setPort(ID::Y, sig);
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cell->fixup_parameters();
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cell->fixup_parameters();
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mi.notify_connect(cell, ID::Y, sig_orig, sig);
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mi.notify_connect(cell, ID::Y, sig_orig, sig);
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mi.sigmap.set(module);
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did_something = true;
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did_something = true;
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}
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}
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@ -591,9 +595,6 @@ struct WreduceWorker
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Wire *nw = module->addWire(module->uniquify(IdString(w->name.str() + "_wreduce")), GetSize(w) - unused_top_bits);
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Wire *nw = module->addWire(module->uniquify(IdString(w->name.str() + "_wreduce")), GetSize(w) - unused_top_bits);
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module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
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module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
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module->swap_names(w, nw);
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module->swap_names(w, nw);
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for (auto bit : mi.sigmap(SigSpec(w).extract(GetSize(nw), unused_top_bits)))
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mi.database.erase(bit);
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mi.sigmap.set(module);
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mi.notify_connect(module, SigSig(nw, SigSpec(w).extract(0, GetSize(nw))));
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mi.notify_connect(module, SigSig(nw, SigSpec(w).extract(0, GetSize(nw))));
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}
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}
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}
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}
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