mirror of https://github.com/YosysHQ/yosys.git
modtools, wreduce: check_db sanity check
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c75d80905a
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@ -297,6 +297,13 @@ struct ModIndex : public RTLIL::Monitor
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return info->ports;
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return info->ports;
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}
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}
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void check_db()
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{
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for (auto &it : database) {
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log_assert(database.find(it.first) != database.end());
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}
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}
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void dump_db()
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void dump_db()
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{
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{
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log("--- ModIndex Dump ---\n");
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log("--- ModIndex Dump ---\n");
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@ -489,6 +489,7 @@ struct WreduceWorker
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for (auto w : module->wires())
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for (auto w : module->wires())
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complete_wires.insert(mi.sigmap(w));
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complete_wires.insert(mi.sigmap(w));
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mi.dump_db();
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for (auto w : module->selected_wires())
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for (auto w : module->selected_wires())
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{
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{
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int unused_top_bits = 0;
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int unused_top_bits = 0;
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@ -496,6 +497,8 @@ struct WreduceWorker
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if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0)
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if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0)
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continue;
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continue;
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log_debug("wire %s\n", w->name);
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mi.check_db();
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for (int i = GetSize(w)-1; i >= 0; i--) {
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for (int i = GetSize(w)-1; i >= 0; i--) {
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SigBit bit(w, i);
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SigBit bit(w, i);
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auto info = mi.query(bit);
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auto info = mi.query(bit);
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