Revert "Temporarily revert #6101 and #6077"

tests/techmap/abc_new.ys

@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module sub(input a, b, c, output y);
+  assign y = (a & b) | c;
+endmodule
+module top(input a, b, c, d, output y, z);
+  assign z = (a ^ b) & d;
+  sub s_i (.a(a), .b(b), .c(c), .y(y));
+endmodule
+EOT
+hierarchy -top top
+techmap
+abc_new -liberty ../liberty/normal.lib -liberty ../liberty/dff.lib
+

tests/techmap/xaiger2-5169.ys

@@ -56,5 +56,5 @@ endmodule
 
 EOF
 
-logger -expect error "Malformed design" 1
+logger -expect error "Cannot find existing box cell" 1
 abc_new -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib