mirror of https://github.com/YosysHQ/yosys.git
Work around `std::reverse` miscompilation with empty range
This causes problems when compiling with fuzzing instrumenation enabled.
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@ -286,6 +286,7 @@ struct RTLILFrontendWorker {
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if (width > MAX_CONST_WIDTH)
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if (width > MAX_CONST_WIDTH)
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error("Constant width %lld out of range before `%s`.", width, error_token());
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error("Constant width %lld out of range before `%s`.", width, error_token());
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bits.reserve(width);
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bits.reserve(width);
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int start_idx = idx;
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while (true) {
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while (true) {
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RTLIL::State bit;
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RTLIL::State bit;
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switch (line[idx]) {
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switch (line[idx]) {
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@ -300,8 +301,9 @@ struct RTLILFrontendWorker {
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bits.push_back(bit);
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bits.push_back(bit);
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++idx;
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++idx;
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}
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}
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done:
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done:
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std::reverse(bits.begin(), bits.end());
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if (start_idx < idx)
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std::reverse(bits.begin(), bits.end());
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if (GetSize(bits) > width)
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if (GetSize(bits) > width)
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bits.resize(width);
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bits.resize(width);
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