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Another typo
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@@ -68,7 +68,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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generate
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if (IS_PRE_INVERTED)
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if (IS_CLR_INVERTED)
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
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else
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));
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