Addings tests for #1836 and #3205

tests/arch/ecp5/bug1836.ys

@@ -0,0 +1,31 @@
+read_verilog <<EOT
+module dds(input clk, output reg [15:0] signal1, output reg [15:0] signal2);
+	reg [9:0] phase_accumulator_1;
+	reg [9:0] phase_accumulator_2;
+	reg [15:0] sine_table [0:255];
+
+	initial begin
+		$readmemh("bug1836.mem",sine_table);
+	end
+
+	always @(posedge clk) begin
+		phase_accumulator_1 <= phase_accumulator_1 + 1;
+		phase_accumulator_2 <= phase_accumulator_2 + 2;
+	end
+
+	always @(posedge clk) begin
+		signal1 <= sine_table[phase_accumulator_1[9:2]];
+		//signal2 <= sine_table[phase_accumulator_2[9:2]];
+	end
+
+	//comment out this always block below to test for single port read
+	always @(posedge clk) begin
+		//signal1 <= sine_table[phase_accumulator_1[9:2]];
+		signal2 <= sine_table[phase_accumulator_2[9:2]];
+	end
+
+endmodule
+EOT
+
+synth_ecp5 -top dds
+select -assert-count 1 t:DP16KD