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verific: Improve logic generated for SVA value change expressions
The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation
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@@ -0,0 +1,51 @@
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module top (
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input clk
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);
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reg [7:0] counter = 0;
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reg a = 0;
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reg b = 1;
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reg c;
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wire a_fell; assign a_fell = $fell(a, @(posedge clk));
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wire a_rose; assign a_rose = $rose(a, @(posedge clk));
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wire a_stable; assign a_stable = $stable(a, @(posedge clk));
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wire b_fell; assign b_fell = $fell(b, @(posedge clk));
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wire b_rose; assign b_rose = $rose(b, @(posedge clk));
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wire b_stable; assign b_stable = $stable(b, @(posedge clk));
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wire c_fell; assign c_fell = $fell(c, @(posedge clk));
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wire c_rose; assign c_rose = $rose(c, @(posedge clk));
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wire c_stable; assign c_stable = $stable(c, @(posedge clk));
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always @(posedge clk) begin
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counter <= counter + 1;
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case (counter)
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0: begin
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assert property ( $fell(a) && !$rose(a) && !$stable(a));
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assert property (!$fell(b) && $rose(b) && !$stable(b));
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assert property (!$fell(c) && !$rose(c) && $stable(c));
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a <= 1; b <= 1; c <= 1;
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end
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1: begin a <= 0; b <= 1; c <= 'x; end
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2: begin
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assert property ( $fell(a) && !$rose(a) && !$stable(a));
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assert property (!$fell(b) && !$rose(b) && $stable(b));
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assert property (!$fell(c) && !$rose(c) && !$stable(c));
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a <= 0; b <= 0; c <= 0;
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end
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3: begin a <= 0; b <= 1; c <= 'x; end
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4: begin
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assert property (!$fell(a) && !$rose(a) && $stable(a));
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assert property (!$fell(b) && $rose(b) && !$stable(b));
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assert property (!$fell(c) && !$rose(c) && !$stable(c));
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a <= 'x; b <= 'x; c <= 'x;
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end
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5: begin a <= 0; b <= 1; c <= 'x; counter <= 0; end
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endcase;
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end
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endmodule
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