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Make test without iopads

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This commit is contained in:
Miodrag Milanovic
2019-12-28 16:22:24 +01:00
parent 509da7ed1a
commit a82c701668
17 changed files with 51 additions and 51 deletions
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tests/arch/xilinx/logic.ys
+1 -1
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@@ -1,7 +1,7 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module