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Remove trailing whitespaces
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@@ -3,7 +3,7 @@ read_verilog <<EOT
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module uut(
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input a,
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output y, z
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);
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);
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assign y = a == a;
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assign z = a != a;
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endmodule
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@@ -3,7 +3,7 @@ read_verilog <<EOT
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module uut(
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input a, b, c, d,
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output y
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);
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);
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assign y = a ? (a ? b : c) : d;
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endmodule
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