Merge pull request #6083 from YosysHQ/release/v0.68

Release version 0.68

CHANGELOG

@@ -2,9 +2,22 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.67 .. Yosys 0.68-dev
+Yosys 0.68 .. Yosys 0.69-dev
 --------------------------
 
+Yosys 0.67 .. Yosys 0.68
+--------------------------
+
+ * New commands and options
+    - Added "symfpu" and "symfpu_convert" passes.
+    - Removed "-fast" option from "abc" pass.
+    - Removed "flowmap" pass and "-flowmap" from "synth"
+      and "synth_ice40" passes.
+    - Removed "-wideports" option from "read_aiger" pass.
+
+ * Various
+    - nexus: fix Radiant netlist compatibility.
+
 Yosys 0.66 .. Yosys 0.67
 --------------------------
  * Various

cmake/YosysVersionData.cmake

@@ -1,2 +1,2 @@
 set(YOSYS_VERSION_MAJOR 0)
-set(YOSYS_VERSION_MINOR 67)
+set(YOSYS_VERSION_MINOR 68)

docs/source/conf.py

@@ -6,7 +6,7 @@ import os
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2026 YosysHQ GmbH'
-yosys_ver = "0.67"
+yosys_ver = "0.68"
 
 # select HTML theme
 html_theme = 'furo-ys'

tests/alumacc/cmp_merge.ys

@@ -40,4 +40,3 @@ EOT
 hierarchy
 wreduce
 equiv_opt -assert alumacc
-

tests/arch/nexus/dsp_equiv.sv

@@ -27,7 +27,7 @@ endmodule
 module mul_pipe_u (input clk, input [8:0] a, b, output reg [17:0] y);
 	reg [8:0] a_r;
 	reg [8:0] b_r;
-	always @(posedge clk) begin 
+	always @(posedge clk) begin
 		a_r <= a;
 		b_r <= b;
 		y <= a_r * b_r;

tests/arch/nexus/pipe_mul.sv

@@ -153,4 +153,4 @@ module mul18_two_clock (
 	always_ff @(posedge clk0) a_r <= a;
 	always_ff @(posedge clk1) b_r <= b;
 	assign y = a_r * b_r;
-endmodule
+endmodule

tests/arch/nexus/pipe_mul.ys

@@ -71,4 +71,4 @@ design -load pristine
 hierarchy -top mul18_two_clock
 synth_nexus -family lifcl -top mul18_two_clock
 select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS
-select -assert-min 1 t:FD1P3*
+select -assert-min 1 t:FD1P3*

tests/opt/opt_muxtree_port_reconverge.ys

@@ -17,7 +17,7 @@ module \top
     connect \S \b
     connect \Y \y
   end
-  
+
   attribute \full_case 1
   cell $pmux \pmux
     parameter \WIDTH 1
@@ -27,7 +27,7 @@ module \top
     connect \S { \n_a \s }
     connect \Y \q
   end
-  
+
   attribute \full_case 1
   cell $not \not
     parameter \A_SIGNED 0

tests/symfpu/edges.sv

@@ -147,7 +147,7 @@ module edges(input clk);
     wire lhs_norm = a_norm;
     wire lhs_subnorm = a_subnorm;
     wire lhs_finite = a_finite;
-    
+
     wire rhs_sign = b_sign;
     wire [30:0] rhs_unsigned = b_unsigned;
     wire [7:0] rhs_exp = b_exp;

tests/techmap/dfflibmap_resetval_clobber.ys

@@ -10,4 +10,4 @@ flatten -noscopeinfo
 opt_clean
 
 select -assert-count 1 t:* top %i
-select -assert-count 1 t:$_DFF_PP0_ top %i
+select -assert-count 1 t:$_DFF_PP0_ top %i

tests/various/hierarchy_recursive.v

@@ -1,3 +1,3 @@
 module top(input x, output y);
 top top_i(.x(x), .y(y));
-endmodule
+endmodule