mirror of https://github.com/YosysHQ/yosys.git
Merge 8a9ae31d34 into 07a615a283
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commit
a57e3a4e73
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@ -196,7 +196,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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for (auto &operand : muxed_operands) {
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operand.sig.extend_u0(max_width, operand.is_signed);
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if (operand.sign != muxed_operands[0].sign)
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operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
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operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed, mux->get_src_attribute()));
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}
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for (const auto& p : ports) {
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@ -241,9 +241,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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SigSpec mux_to_oper;
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if (GetSize(shared_pmux_s) == 1) {
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mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s, mux->get_src_attribute());
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} else {
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mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s, mux->get_src_attribute());
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}
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if (shared_op->type.in(ID($alu))) {
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@ -0,0 +1,47 @@
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read_rtlil <<EOT
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module \top
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wire width 4 input 1 \a
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wire width 4 input 2 \b
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wire width 4 input 3 \c
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wire input 4 \sel
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wire width 4 \add0_y
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wire width 4 \add1_y
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wire width 4 output 5 \y
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cell $add \add0
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parameter \A_SIGNED 0
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parameter \A_WIDTH 4
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parameter \B_SIGNED 0
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 4
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connect \A \a
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connect \B \b
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connect \Y \add0_y
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end
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cell $add \add1
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parameter \A_SIGNED 0
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parameter \A_WIDTH 4
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parameter \B_SIGNED 0
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 4
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connect \A \a
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connect \B \c
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connect \Y \add1_y
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end
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attribute \src "opt_share_mux_src"
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cell $mux \mux
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parameter \WIDTH 4
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connect \A \add0_y
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connect \B \add1_y
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connect \S \sel
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connect \Y \y
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end
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end
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EOT
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opt_share
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select -assert-count 1 t:$add
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select -assert-count 2 t:$mux a:src=opt_share_mux_src %i
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