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es3298 2026-07-28 16:28:17 +02:00 committed by GitHub
commit a57e3a4e73
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2 changed files with 50 additions and 3 deletions

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@ -196,7 +196,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
for (auto &operand : muxed_operands) {
operand.sig.extend_u0(max_width, operand.is_signed);
if (operand.sign != muxed_operands[0].sign)
operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed, mux->get_src_attribute()));
}
for (const auto& p : ports) {
@ -241,9 +241,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
SigSpec mux_to_oper;
if (GetSize(shared_pmux_s) == 1) {
mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s, mux->get_src_attribute());
} else {
mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s, mux->get_src_attribute());
}
if (shared_op->type.in(ID($alu))) {

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@ -0,0 +1,47 @@
read_rtlil <<EOT
module \top
wire width 4 input 1 \a
wire width 4 input 2 \b
wire width 4 input 3 \c
wire input 4 \sel
wire width 4 \add0_y
wire width 4 \add1_y
wire width 4 output 5 \y
cell $add \add0
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \a
connect \B \b
connect \Y \add0_y
end
cell $add \add1
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \a
connect \B \c
connect \Y \add1_y
end
attribute \src "opt_share_mux_src"
cell $mux \mux
parameter \WIDTH 4
connect \A \add0_y
connect \B \add1_y
connect \S \sel
connect \Y \y
end
end
EOT
opt_share
select -assert-count 1 t:$add
select -assert-count 2 t:$mux a:src=opt_share_mux_src %i