luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

hierarchy: fix twines

This commit is contained in:
Emil J. Tywoniak 2026-06-24 11:53:51 +02:00
parent a3e982a5e2
commit a4e7c5c4e4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/hierarchy/hierarchy.cc
View File

@ -1579,7 +1579,7 @@ struct HierarchyPass : public Pass {
if (!conn.second.is_fully_const() || !w->port_input || w->port_output) if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", module, cell, log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", module, cell,
design->twines.str(conn.first).data(), GetSize(conn.second), GetSize(sig)); design->twines.unescaped_str(conn.first).data(), GetSize(conn.second), GetSize(sig));
cell->setPort(conn.first, sig); cell->setPort(conn.first, sig);
} }