luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

intel_alm: direct M10K instantiation

Browse Source 
This reverts commit a3a90f6377.
This commit is contained in:
Dan Ravensloft
2020-07-27 15:39:06 +02:00
committed by Marcelina Kościelnicka
parent 62311b7ec0
commit a2fb84fd0c
8 changed files with 133 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files
techlibs/intel_alm/common/bram_m10k_map.v
-31
View File
@@ -1,31 +0,0 @@
module __MISTRAL_M10K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
output [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_A-1:0] A1EN, B1EN;
altsyncram #(
.operation_mode("dual_port"),
.ram_block_type("m10k"),
.widthad_a(CFG_ABITS),
.width_a(CFG_DBITS),
.widthad_b(CFG_ABITS),
.width_b(CFG_DBITS),
) _TECHMAP_REPLACE_ (
.address_a(A1ADDR),
.data_a(A1DATA),
.wren_a(A1EN),
.address_b(B1ADDR),
.q_b(B1DATA),
.clock0(CLK1),
.clock1(CLK1)
);
endmodule