gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

tests/lut/.gitignore

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+*.log

tests/lut/check_map.ys

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+design -save preopt
+
+simplemap
+techmap -map +/gate2lut.v -D LUT_WIDTH=4
+select -assert-count 1 t:$lut
+design -stash postopt
+
+design -copy-from preopt -as preopt top
+design -copy-from postopt -as postopt top
+equiv_make preopt postopt equiv
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert

tests/lut/map_and.v

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+module top(...);
+    input a, b;
+    output y;
+    assign y = a&b;
+endmodule

tests/lut/map_mux.v

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+module top(...);
+    input a, b, s;
+    output y;
+    assign y = s?a:b;
+endmodule

tests/lut/map_not.v

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+module top(...);
+    input a;
+    output y;
+    assign y = ~a;
+endmodule

tests/lut/map_or.v

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+module top(...);
+    input a, b;
+    output y;
+    assign y = a|b;
+endmodule

tests/lut/map_xor.v

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+module top(...);
+    input a, b;
+    output y;
+    assign y = a^b;
+endmodule

tests/lut/run-test.sh

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+#!/bin/bash
+set -e
+for x in *.v; do
+  echo "Running $x.."
+  ../../yosys -q -s check_map.ys -l ${x%.v}.log $x
+done