write_xaiger: add support and test for (* keep *) on wires

tests/techmap/abc9.ys

@@ -38,3 +38,16 @@ abc9 -lut 4
 design -load gold
 scratchpad -copy abc9.script.flow3 abc9.script
 abc9 -lut 4
+
+design -reset
+read_verilog <<EOT
+module top(input a, b, output o);
+(* keep *) wire w = a & b;
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 2 t:$lut