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Unify verilog style

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This commit is contained in:
Miodrag Milanovic
2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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tests/arch/common/mul.v
+5 -7
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@@ -1,11 +1,9 @@
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule