Fixed mem assignment in left-hand-side concatenation

tests/simple/memory.v

@@ -264,3 +264,16 @@ module memtest11(clk, wen, waddr, raddr, wdata, rdata);
 	end
 endmodule
 
+// ----------------------------------------------------------
+
+module memtest12 (
+   input clk,
+   input [1:0] adr,
+   input [1:0] din,
+   output reg [1:0] q
+);
+   reg [1:0] ram [3:0];
+   always@(posedge clk)
+     {ram[adr], q} <= {din, ram[adr]};
+endmodule
+