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Docs: Fix nested list on build_verific page

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Krystine Sherwin
2024-08-27 10:06:26 +12:00
parent 7d63fdd88e
commit 98d26bdd2c
1 changed files with 4 additions and 2 deletions
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docs/source/yosys_internals/extending_yosys/build_verific.rst
+4 -2
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@@ -81,8 +81,10 @@ The following features, along with their corresponding Yosys build parameters,
are required for the Yosys-Verific patch:
* RTL elaboration with
* SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
* VHDL support with ``ENABLE_VERIFIC_VHDL``.
* SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
* VHDL support with ``ENABLE_VERIFIC_VHDL``.
* Hierarchy tree support and static elaboration with
``ENABLE_VERIFIC_HIER_TREE``.