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Allow whitebox modules to be overwritten

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This commit is contained in:
Eddie Hung
2019-08-07 16:40:24 -07:00
parent 9962e6fc1a
commit 9776084eda
2 changed files with 1 additions and 3 deletions
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techlibs/ice40/tests/test_arith.ys
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@@ -8,8 +8,6 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
delete A:whitebox # Necessary since whiteboxes cannot
# be overwritten...
synth_ice40 -top gate
read_verilog test_arith.v