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Merge pull request #1203 from whitequark/write_verilog-zero-width-values

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write_verilog: dump zero width constants correctly
This commit is contained in:
Clifford Wolf
2019-07-18 15:31:27 +02:00
committed by GitHub
parent 56c00e871f 4ff44d85a5
commit 927f0caa9d
1 changed files with 2 additions and 1 deletions
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backends/verilog/verilog_backend.cc
+2 -1
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@@ -189,7 +189,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
if (width < 0) if (width < 0)
width = data.bits.size() - offset; width = data.bits.size() - offset;
if (width == 0) { if (width == 0) {
f << "\"\""; // See IEEE 1364-2005 Clause 5.1.14.
f << "{0{1'b0}}";
return; return;
} }
if (nostr) if (nostr)