luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

synth_*: no need to explicitly read +/abc9_model.v

Browse Source
This commit is contained in:
Eddie Hung
2020-05-14 10:33:56 -07:00
parent 63246a5c0e
commit 8fbb55f4ab
4 changed files with 3 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
techlibs/xilinx/synth_xilinx.cc
+1 -1
View File
@@ -616,7 +616,7 @@ struct SynthXilinxPass : public ScriptPass
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W";
if (active_design && active_design->scratchpad.count(k))