mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-08-29 01:24:25 +02:00
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
This commit is contained in:
@@ -0,0 +1,4 @@
|
||||
read_verilog opt_expr_cmp.v
|
||||
equiv_opt -assert opt_expr -fine
|
||||
design -load postopt
|
||||
select -assert-count 0 t:$gt t:$ge t:$lt t:$le
|
||||
Reference in New Issue
Block a user