Fix setting bits of parameters in setundef pass

This commit also adds test that verifies correctness of this change.

tests/various/setundef.sv

@@ -0,0 +1,10 @@
+module foo #(parameter [1:0] a) (output [1:0] o);
+	assign o = a;
+endmodule
+
+module top(output [1:0] o);
+	foo #(2'b0x) foo(o);
+	always_comb begin
+		assert(o == 2'b00);
+	end
+endmodule

tests/various/setundef.ys

@@ -0,0 +1,8 @@
+read_verilog -sv setundef.sv
+setundef -zero -params
+hierarchy -top top
+flatten
+proc
+async2sync
+write_json
+sat -seq 5 -prove-asserts