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Revert "submod to bitty rather bussy, for bussy wires used as input and output"

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This reverts commit cba3073026.
This commit is contained in:
Eddie Hung
2019-11-27 00:48:22 -08:00
parent 969f511415
commit 8c813632b6
2 changed files with 76 additions and 42 deletions
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tests/various/submod.ys
+5 -2
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@@ -52,8 +52,10 @@ sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module top(input d, c, (* init = 1'b1 *) output reg q);
(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q));
module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
DFF s2(.D(d), .C(c), .Q(q[0]));
DFF s3(.D(d), .C(c), .Q(q[2]));
endmodule
module DFF(input D, C, output Q);
@@ -62,6 +64,7 @@ endmodule
EOT
hierarchy -top top
proc
submod
dffinit -ff DFF Q INIT