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opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
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@ -1206,8 +1206,13 @@ skip_fine_alu:
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replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y);
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goto next_cell;
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}
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if (a[i] == b[i])
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continue;
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if (keepdc) {
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if (!a[i].is_wire() && !b[i].is_wire() && a[i].data != RTLIL::State::Sx && b[i].data != RTLIL::State::Sx && a[i] == b[i])
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continue;
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} else {
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if (a[i] == b[i])
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continue;
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}
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new_a.append(a[i]);
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new_b.append(b[i]);
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}
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