luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix

This commit is contained in:
Stan Lee 2026-04-16 15:35:11 -07:00
parent 2667070cdd
commit 85fc4fdc0e
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/silimate/reg_rename.cc
View File

@ -165,7 +165,7 @@ struct RegRenameInstance {
for (int i = 0; i < GetSize(oldWire); i++)
bit_map[SigBit(oldWire, i)] = SigBit(targetWire, bitIndex + i);
removeWireCache.insert(oldWire);
wireRemoveCache.insert(oldWire);
}
}
}
@ -183,7 +183,7 @@ struct RegRenameInstance {
}
// Delete the old unused wires
module->remove(removeWireCache);
module->remove(wireRemoveCache);
}
void process_all(dict<std::pair<std::string, std::string>, int> &vcd_reg_widths)