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opt_expr: avoid multiple drivers issue #4792 in combined assign tests

This commit is contained in:
Emil J. Tywoniak 2025-12-19 18:32:06 +01:00
parent 772d821fb0
commit 856d455065
1 changed files with 10 additions and 5 deletions
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15
tests/opt/opt_expr_combined_assign.ys
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@ -1,7 +1,8 @@
read_verilog -sv <<EOT
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a = 8'b0;
a |= i;
a |= j;
end
@ -17,8 +18,9 @@ select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a = 8'b0;
a += i;
a += j;
end
@ -34,8 +36,9 @@ select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a = 8'b0;
a ^= i;
a ^= j;
end
@ -51,8 +54,9 @@ select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a = 8'b0;
a -= i;
a -= j;
end
@ -68,8 +72,9 @@ select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b11111111;
wire[8:0] a;
initial begin
a = 8'b11111111;
a &= i;
a &= j;
end