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Fixed cellaigs port extending

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This commit is contained in:
Clifford Wolf
2015-06-10 07:16:30 +02:00
parent 66f9ee412a
commit 85287295b2
3 changed files with 11 additions and 3 deletions
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passes/tests/test_cell.cc
+7
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@@ -536,6 +536,9 @@ struct TestCellPass : public Pass {
log(" -simlib\n");
log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
log("\n");
log(" -aig\n");
log(" instead of calling \"techmap\", call \"aig\"\n");
log("\n");
log(" -muxdiv\n");
log(" when creating test benches with dividers, create an additional mux\n");
log(" to mask out the division-by-zero case\n");
@@ -600,6 +603,10 @@ struct TestCellPass : public Pass {
techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
continue;
}
if (args[argidx] == "-aig") {
techmap_cmd = "aig";
continue;
}
if (args[argidx] == "-muxdiv") {
muxdiv = true;
continue;