luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

Progress on presentation

Browse Source
This commit is contained in:
Clifford Wolf
2014-01-28 06:51:50 +01:00
parent a3ac6b6f47
commit 842ca2f011
2 changed files with 69 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
manual/PRESENTATION_Intro.tex
+14 -7
View File
@@ -5,6 +5,8 @@
\sectionpage
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Representations of (digital) Circuits}
\begin{frame}[t]{\subsecname}
@@ -18,18 +20,23 @@
\item Non-graphical
\begin{itemize}
\item \alert<3>{Netlists}
\item \alert<4>{Hardware Description Language}
\item \alert<4>{Hardware Description Languages (HDLs)}
\end{itemize}
\end{itemize}
\bigskip
\begin{block}{Definition}
\only<1>{Schematic Diagrams are ... TBD}
\only<2>{Physical Layouts are ... TBD}
\only<3>{Netlists are ... TBD}
\only<4>{Hardware Description Languages are ... TBD}
\begin{block}{Definition:
\only<1>{Schematic Diagram}%
\only<2>{Physical Layout}%
\only<3>{Netlists}%
\only<4>{Hardware Description Languages (HDLs)}}
\only<1>{TBD}
\only<2>{TBD}
\only<3>{TBD}
\only<4>{TBD}
\end{block}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Levels of Abstraction for Digital Circuits}
@@ -81,10 +88,10 @@
\end{block}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Digital Circuit Synthesis}
\begin{frame}{\subsecname}
\end{frame}