mirror of https://github.com/YosysHQ/yosys.git
Add initial single SBY file
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834c84f84d
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[tasks]
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stage_1_init
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stage_1_fv
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stage_2_init
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stage_2_fv
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[options]
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stage_1_init:
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mode prep
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expect unknown
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make_model prep
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stage_1_fv:
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mode cover
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depth 24
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[engines]
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stage_1_init stage_2_init:
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none
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stage_1_fv stage_2_fv:
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smtbmc
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[script]
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stage_1_init:
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verific -formal dut.sv
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[files]
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stage_1_init: dut.sv
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stage_2_init:
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stage_1/engine_0/trace0.yw
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stage_1_init.il
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