reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-28 17:14:11 +02:00

This commit is contained in:

Udi Finkelstein

2018-06-05 18:00:06 +03:00

committed by

Unknown

parent 2b9c75f8e3

commit 80d9d15f1c

2 changed files with 1 additions and 0 deletions

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				`@@ -0,0 +1 @@`
				`read_verilog -sv reg_wire_error.sv`