mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #78 from williamzhu17/extract_reduce-tests
extract_reduce tests and removed XNOR functionality from extract_reduce
This commit is contained in:
Akash Levy
GitHub
commit
809a38a597
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@ -30,7 +30,6 @@ struct ExtractReducePass : public Pass
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And,
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Or,
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Xor,
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Xnor,
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Mux
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};
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@ -51,8 +50,8 @@ struct ExtractReducePass : public Pass
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log("to map the design to only $_AND_ cells, run extract_reduce, map the remaining\n");
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log("parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.\n");
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log("\n");
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log("Silimate has modified this pass to support word-level cells ($and, $or, $xor,\n");
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log("and $xnor) as well as the single-bit cells ($_AND_, $_OR_, $_XOR_, and $_XNOR_).\n");
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log("Silimate has modified this pass to support word-level cells ($and, $or, \n");
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log("and $xor) as well as the single-bit cells ($_AND_, $_OR_, and $_XOR_).\n");
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log("Mux cells ($mux, $_MUX_) can also be reduced to $pmux cells with the mods.\n");
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log("\n");
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log(" -allow-off-chain\n");
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@ -86,12 +85,10 @@ struct ExtractReducePass : public Pass
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return (cell->type == ID($_AND_) && gt == GateType::And) ||
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(cell->type == ID($_OR_) && gt == GateType::Or) ||
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(cell->type == ID($_XOR_) && gt == GateType::Xor) ||
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(cell->type == ID($_XNOR_) && gt == GateType::Xnor) ||
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(cell->type == ID($_MUX_) && gt == GateType::Mux) ||
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(cell->type == ID($and) && IsSingleBit(cell) && gt == GateType::And) ||
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(cell->type == ID($or) && IsSingleBit(cell) && gt == GateType::Or) ||
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(cell->type == ID($xor) && IsSingleBit(cell) && gt == GateType::Xor) ||
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(cell->type == ID($xnor) && IsSingleBit(cell) && gt == GateType::Xnor) ||
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(cell->type == ID($mux) && IsSingleBit(cell) && gt == GateType::Mux);
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}
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@ -177,8 +174,6 @@ struct ExtractReducePass : public Pass
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gt = GateType::Or;
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else if (cell->type == ID($_XOR_))
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gt = GateType::Xor;
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else if (cell->type == ID($_XNOR_))
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gt = GateType::Xnor;
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else if (cell->type == ID($_MUX_))
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gt = GateType::Mux;
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else if (cell->type == ID($and) && IsSingleBit(cell))
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@ -187,8 +182,6 @@ struct ExtractReducePass : public Pass
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gt = GateType::Or;
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else if (cell->type == ID($xor) && IsSingleBit(cell))
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gt = GateType::Xor;
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else if (cell->type == ID($xnor) && IsSingleBit(cell))
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gt = GateType::Xnor;
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else if (cell->type == ID($mux) && IsSingleBit(cell))
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gt = GateType::Mux;
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else
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@ -355,7 +348,7 @@ struct ExtractReducePass : public Pass
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SigSpec input, sel;
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for (auto it : sources) {
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bool cond;
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if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor) || head_cell->type == ID($_XNOR_) || head_cell->type == ID($xnor))
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if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor))
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cond = it.second & 1;
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else
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cond = it.second != 0;
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@ -375,8 +368,6 @@ struct ExtractReducePass : public Pass
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module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor)) {
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module->addReduceXor(NEW_ID2_SUFFIX("reduce_xor"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else if (head_cell->type == ID($_XNOR_) || head_cell->type == ID($xnor)) {
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module->addReduceXnor(NEW_ID2_SUFFIX("reduce_xnor"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else if (head_cell->type == ID($_MUX_) || head_cell->type == ID($mux)) {
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module->addPmux(NEW_ID2_SUFFIX("pmux"), State::Sx, input, sel, output, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else {
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@ -0,0 +1,950 @@
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###################################################################
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# Extract Reduce AND Gates Tests
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###################################################################
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log -header "Simple AND chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] & a[1] & a[2] & a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "AND chain with constants"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [2:0] a,
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output wire x
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);
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assign x = a[0] & a[1] & a[2] & 1'b1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "AND chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w0, w1, w2, w3;
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assign w0 = a[0] & a[1];
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assign w1 = a[2] & a[3];
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assign w2 = a[4] & a[5];
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assign w3 = w0 & w1;
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assign x = w2 & w3;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
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design -reset
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log -pop
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log -header "No off-chain for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w0, w1, w2;
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assign w0 = a[0] & a[1];
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assign w1 = w0 & a[2];
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assign w2 = w1 & a[3];
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assign x = w2 & a[4];
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// Off-chain use of w1
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assign y = w1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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select -assert-count 2 t:$reduce_and
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# Check that both gates are 3 bits wide
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select -assert-none t:$reduce_and r:A_WIDTH!=3 %i
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design -reset
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log -pop
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log -header "Allow off-chain for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w0, w1, w2;
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assign w0 = a[0] & a[1];
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assign w1 = w0 & a[2];
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assign w2 = w1 & a[3];
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assign x = w2 & a[4];
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// Off-chain use of w1
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assign y = w1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that only one gate has a width of 5 and one gate has a width of 3
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select -assert-count 1 t:$reduce_and r:A_WIDTH=5 %i
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select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
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design -reset
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log -pop
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log -header "No off-chain with branches for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
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assign x = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that both gates are 6 bits wide
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select -assert-none t:$reduce_and r:A_WIDTH!=6 %i
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design -reset
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log -pop
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log -header "Allow off-chain with branches for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
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assign x = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that only one gate has a width of 11 and one gate has a width of 6
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select -assert-count 1 t:$reduce_and r:A_WIDTH=11 %i
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select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
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design -reset
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log -pop
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###################################################################
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# Extract Reduce OR Gates Tests
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###################################################################
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log -header "Simple OR chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] | a[1] | a[2] | a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
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select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "OR chain with constants"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] | a[1] | a[2] | 1'b1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
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select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "OR chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w0, w1, w2, w3;
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assign w0 = a[0] | a[1];
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assign w1 = a[2] | a[3];
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assign w2 = a[4] | a[5];
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assign w3 = w0 | w1;
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assign x = w2 | w3;
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endmodule
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EOF
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check -assert
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|
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# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
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# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
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opt_clean
|
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|
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# Check final design has correct number of gates and inputs
|
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
|
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select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
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|
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design -reset
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log -pop
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|
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|
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|
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log -header "No off-chain OR"
|
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log -push
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design -reset
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read_verilog <<EOF
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module top (
|
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input wire [4:0] a,
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output wire x,
|
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output wire y
|
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);
|
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wire w0, w1, w2;
|
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|
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assign w0 = a[0] | a[1];
|
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assign w1 = w0 | a[2];
|
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assign w2 = w1 | a[3];
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assign x = w2 | a[4];
|
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|
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// Off-chain use of w1
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assign y = w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$or
|
||||
select -assert-count 2 t:$reduce_or
|
||||
|
||||
# Check that both gates are 3 bits wide
|
||||
select -assert-none t:$reduce_or r:A_WIDTH!=3 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
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log -header "Allow off-chain for OR"
|
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log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
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input wire [4:0] a,
|
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output wire x,
|
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output wire y
|
||||
);
|
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wire w0, w1, w2;
|
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|
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assign w0 = a[0] | a[1];
|
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assign w1 = w0 | a[2];
|
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assign w2 = w1 | a[3];
|
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assign x = w2 | a[4];
|
||||
|
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// Off-chain use of w1
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||||
assign y = w1;
|
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endmodule
|
||||
EOF
|
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check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$or
|
||||
select -assert-count 2 t:$reduce_or
|
||||
|
||||
# Check that only one gate has a width of 5 and one gate has a width of 3
|
||||
select -assert-count 1 t:$reduce_or r:A_WIDTH=5 %i
|
||||
select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "No off-chain with branches for OR"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [10:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0;
|
||||
|
||||
assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
|
||||
assign x = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
|
||||
|
||||
// Off-chain use of w0
|
||||
assign y = w0;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$and
|
||||
select -assert-count 2 t:$reduce_or
|
||||
|
||||
# Check that both gates are 6 bits wide
|
||||
select -assert-none t:$reduce_or r:A_WIDTH!=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Allow off-chain with branches for OR"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [10:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0;
|
||||
|
||||
assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
|
||||
assign x = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
|
||||
|
||||
// Off-chain use of w0
|
||||
assign y = w0;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$or
|
||||
select -assert-count 2 t:$reduce_or
|
||||
|
||||
# Check that only one gate has a width of 11 and one gate has a width of 6
|
||||
select -assert-count 1 t:$reduce_or r:A_WIDTH=11 %i
|
||||
select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
###################################################################
|
||||
# Extract Reduce XOR Gates Tests
|
||||
###################################################################
|
||||
|
||||
log -header "Simple XOR chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [3:0] a,
|
||||
output wire x
|
||||
);
|
||||
assign x = a[0] ^ a[1] ^ a[2] ^ a[3];
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates and inputs
|
||||
select -assert-count 0 t:$xor
|
||||
select -assert-count 1 t:$reduce_xor
|
||||
select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "XOR chain with constants"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [3:0] a,
|
||||
output wire x
|
||||
);
|
||||
assign x = a[0] ^ a[1] ^ a[2] ^ 1'b1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates and inputs
|
||||
select -assert-count 0 t:$xor
|
||||
select -assert-count 1 t:$reduce_xor
|
||||
select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "XOR chain with multiple branches"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [5:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1, w2, w3;
|
||||
|
||||
assign w0 = a[0] ^ a[1];
|
||||
assign w1 = a[2] ^ a[3];
|
||||
assign w2 = a[4] ^ a[5];
|
||||
assign w3 = w0 ^ w1;
|
||||
assign x = w2 ^ w3;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates and inputs
|
||||
select -assert-count 0 t:$xor
|
||||
select -assert-count 1 t:$reduce_xor
|
||||
select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "No off-chain XOR"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [4:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0, w1, w2;
|
||||
|
||||
assign w0 = a[0] ^ a[1];
|
||||
assign w1 = w0 ^ a[2];
|
||||
assign w2 = w1 ^ a[3];
|
||||
assign x = w2 ^ a[4];
|
||||
|
||||
// Off-chain use of w1
|
||||
assign y = w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$xor
|
||||
select -assert-count 2 t:$reduce_xor
|
||||
|
||||
# Check that both gates are 3 bits wide
|
||||
select -assert-none t:$reduce_xor r:A_WIDTH!=3 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Allow off-chain for XOR"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [4:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0, w1, w2;
|
||||
|
||||
assign w0 = a[0] ^ a[1];
|
||||
assign w1 = w0 ^ a[2];
|
||||
assign w2 = w1 ^ a[3];
|
||||
assign x = w2 ^ a[4];
|
||||
|
||||
// Off-chain use of w1
|
||||
assign y = w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$xor
|
||||
select -assert-count 2 t:$reduce_xor
|
||||
|
||||
# Check that only one gate has a width of 5 and one gate has a width of 3
|
||||
select -assert-count 1 t:$reduce_xor r:A_WIDTH=5 %i
|
||||
select -assert-count 1 t:$reduce_xor r:A_WIDTH=3 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "No off-chain with branches for XOR"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [10:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0;
|
||||
|
||||
assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
|
||||
assign x = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
|
||||
|
||||
// Off-chain use of w0
|
||||
assign y = w0;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$xor
|
||||
select -assert-count 2 t:$reduce_xor
|
||||
|
||||
# Check that both gates are 6 bits wide
|
||||
select -assert-none t:$reduce_xor r:A_WIDTH!=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Allow off-chain with branches for XOR"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [10:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0;
|
||||
|
||||
assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
|
||||
assign x = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
|
||||
|
||||
// Off-chain use of w0
|
||||
assign y = w0;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates
|
||||
select -assert-count 0 t:$xor
|
||||
select -assert-count 2 t:$reduce_xor
|
||||
|
||||
# Check that only one gate has a width of 11 and one gate has a width of 6
|
||||
select -assert-count 1 t:$reduce_xor r:A_WIDTH=11 %i
|
||||
select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
###################################################################
|
||||
# Edge Cases
|
||||
###################################################################
|
||||
|
||||
log -header "Reconvergence"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
output wire y
|
||||
);
|
||||
wire w0, w1, w2, w3, w4, w5, w6;
|
||||
|
||||
assign w0 = a[0] & a[1];
|
||||
assign w1 = a[2] & a[3];
|
||||
assign w2 = w0 & w1;
|
||||
assign w3 = w2 & a[4];
|
||||
assign w4 = w2 & a[5];
|
||||
assign w5 = w3 & a[6];
|
||||
assign w6 = w4 & a[7];
|
||||
assign y = w5 & w6;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates and inputs
|
||||
select -assert-count 0 t:$and
|
||||
select -assert-count 2 t:$reduce_and
|
||||
select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
|
||||
select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Stress test"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a0,
|
||||
input wire [7:0] a1,
|
||||
input wire [7:0] a2,
|
||||
output wire y
|
||||
);
|
||||
wire c0, c1, c2;
|
||||
|
||||
// Stage 0
|
||||
wire s0_w0 = a0[0] & a0[1];
|
||||
wire s0_w1 = a0[2] & a0[3];
|
||||
wire s0_w2 = s0_w0 & s0_w1;
|
||||
wire s0_w3 = s0_w2 & a0[4];
|
||||
wire s0_w4 = a0[0] & a0[5];
|
||||
wire s0_w5 = s0_w3 & a0[6];
|
||||
wire s0_w6 = s0_w4 & a0[7];
|
||||
assign c0 = s0_w5 & s0_w6;
|
||||
|
||||
// Stage 1
|
||||
wire s1_w0 = a1[0] & a1[1];
|
||||
wire s1_w1 = a1[2] & a1[3];
|
||||
wire s1_w2 = s1_w0 & s1_w1;
|
||||
wire s1_w3 = s1_w2 & a1[4];
|
||||
wire s1_w4 = c0 & a1[5];
|
||||
wire s1_w5 = s1_w3 & a1[6];
|
||||
wire s1_w6 = s1_w4 & a1[7];
|
||||
assign c1 = s1_w5 & s1_w6;
|
||||
|
||||
// Stage 2
|
||||
wire s2_w0 = a2[0] & a2[1];
|
||||
wire s2_w1 = a2[2] & a2[3];
|
||||
wire s2_w2 = s2_w0 & s2_w1;
|
||||
wire s2_w3 = s2_w2 & a2[4];
|
||||
wire s2_w4 = c1 & a2[5];
|
||||
wire s2_w5 = s2_w3 & a2[6];
|
||||
wire s2_w6 = s2_w4 & a2[7];
|
||||
assign c2 = s2_w5 & s2_w6;
|
||||
|
||||
assign y = c2;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
extract_reduce
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates and inputs
|
||||
select -assert-count 0 t:$and
|
||||
select -assert-count 1 t:$reduce_and
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Stress test reconvergence"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a0,
|
||||
input wire [7:0] a1,
|
||||
input wire [7:0] a2,
|
||||
output wire y
|
||||
);
|
||||
wire c0, c1, c2;
|
||||
|
||||
// Stage 0
|
||||
wire s0_w0 = a0[0] & a0[1];
|
||||
wire s0_w1 = a0[2] & a0[3];
|
||||
wire s0_w2 = s0_w0 & s0_w1;
|
||||
wire s0_w3 = s0_w2 & a0[4];
|
||||
wire s0_w4 = s0_w2 & a0[5];
|
||||
wire s0_w5 = s0_w3 & a0[6];
|
||||
wire s0_w6 = s0_w4 & a0[7];
|
||||
assign c0 = s0_w5 & s0_w6;
|
||||
|
||||
// Stage 1
|
||||
wire s1_w0 = a1[0] & a1[1];
|
||||
wire s1_w1 = a1[2] & a1[3];
|
||||
wire s1_w2 = s1_w0 & s1_w1;
|
||||
wire s1_w3 = s1_w2 & a1[4];
|
||||
wire s1_w4 = s1_w2 & a1[5];
|
||||
wire s1_w5 = s1_w3 & a1[6];
|
||||
wire s1_w6 = s1_w4 & c0;
|
||||
assign c1 = s1_w5 & s1_w6;
|
||||
|
||||
// Stage 2
|
||||
wire s2_w0 = a2[0] & a2[1];
|
||||
wire s2_w1 = a2[2] & a2[3];
|
||||
wire s2_w2 = s2_w0 & s2_w1;
|
||||
wire s2_w3 = s2_w2 & a2[4];
|
||||
wire s2_w4 = s2_w2 & a2[5];
|
||||
wire s2_w5 = s2_w3 & a2[6];
|
||||
wire s2_w6 = s2_w4 & c1;
|
||||
assign c2 = s2_w5 & s2_w6;
|
||||
|
||||
assign y = c2;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check final design has correct number of gates and inputs
|
||||
select -assert-count 0 t:$and
|
||||
select -assert-count 4 t:$reduce_and
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,584 @@
|
|||
log -header "Simple MUX chain to PMUX"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [2:0] sel,
|
||||
input wire [3:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign x = sel[2] ? a[3] : w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check we got a single pmux with the correct input number
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "MUX chain with constants"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [2:0] sel,
|
||||
input wire [2:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign x = sel[2] ? 1'b1 : w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check we got a single pmux with the correct input number
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "MUX chain with multiple branches"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [2:0] sel,
|
||||
input wire [3:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : a[3];
|
||||
assign x = sel[2] ? w0 : w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check we got a single pmux with the correct input number
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=4 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "MUX chain with multiple uneven branches"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [5:0] sel,
|
||||
input wire [6:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1, w2, w3, w4;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign w2 = sel[2] ? a[3] : w1;
|
||||
assign w3 = sel[3] ? w2 : w4;
|
||||
assign w4 = sel[5] ? a[4] : a[5];
|
||||
assign x = sel[4] ? w3 : a[6];
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check we got a single pmux with the correct input number
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=7 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "No off-chain MUX chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [3:0] sel,
|
||||
input wire [4:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0, w1, w2;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign w2 = sel[2] ? a[3] : w1;
|
||||
assign x = sel[3] ? a[4] : w2;
|
||||
|
||||
// Off-chain use of intermediate wire
|
||||
assign y = w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check we got two pmuxes
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
|
||||
# Check that both pmuxes have input width of 3
|
||||
select -assert-none t:$pmux r:S_WIDTH!=3 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
|
||||
log -header "Allow off-chain MUX chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [3:0] sel,
|
||||
input wire [4:0] a,
|
||||
output wire x,
|
||||
output wire y
|
||||
);
|
||||
wire w0, w1, w2;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign w2 = sel[2] ? a[3] : w1;
|
||||
assign x = sel[3] ? a[4] : w2;
|
||||
|
||||
assign y = w1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean to remove unnecessary wires
|
||||
design -load postopt
|
||||
opt_clean
|
||||
|
||||
# Check we got two pmux
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
|
||||
# Check that one pmux has an input width of 3
|
||||
# and the other has an input width of 5
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=5 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Reconverging tree; no off-chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] sel,
|
||||
input wire [7:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1, w2, w3, w4, w5, w6;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign w2 = sel[2] ? w4 : w1;
|
||||
assign w3 = sel[3] ? w2 : w5;
|
||||
assign w4 = sel[6] ? a[3] : w6;
|
||||
assign w5 = sel[5] ? a[5] : w4;
|
||||
assign w6 = sel[7] ? a[7] : a[4];
|
||||
assign x = sel[4] ? a[6] : w3;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean and opt_reduce to remove unnecessary cells
|
||||
design -load postopt
|
||||
opt_clean
|
||||
opt_reduce
|
||||
|
||||
# Check we got one pmux with correct number of inputs
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Reconverging tree; yes off-chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] sel,
|
||||
input wire [7:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1, w2, w3, w4, w5, w6;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign w2 = sel[2] ? w4 : w1;
|
||||
assign w3 = sel[3] ? w2 : w5;
|
||||
assign w4 = sel[6] ? a[3] : w6;
|
||||
assign w5 = sel[5] ? a[5] : w4;
|
||||
assign w6 = sel[7] ? a[7] : a[4];
|
||||
assign x = sel[4] ? a[6] : w3;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean and opt_reduce to remove unnecessary cells
|
||||
design -load postopt
|
||||
opt_clean
|
||||
opt_reduce
|
||||
|
||||
# Check we got one pmux with correct number of inputs
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=8 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Reusing select inputs"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [5:0] sel,
|
||||
input wire [7:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1, w2, w3, w4, w5, w6;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign w2 = sel[2] ? w4 : w1;
|
||||
assign w3 = sel[3] ? w2 : w5;
|
||||
assign w4 = sel[2] ? a[3] : w6;
|
||||
assign w5 = sel[5] ? a[5] : w4;
|
||||
assign w6 = sel[4] & sel[1] ? a[7] : a[4];
|
||||
assign x = sel[4] ? a[6] : w3;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean and opt_reduce to remove unnecessary cells
|
||||
design -load postopt
|
||||
opt_clean
|
||||
opt_reduce
|
||||
|
||||
# Check we got one pmux with correct number of inputs
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Using outputs as select inputs"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [5:0] sel,
|
||||
input wire [7:0] a,
|
||||
output wire x
|
||||
);
|
||||
wire w0, w1, w2, w3, w4, w5, w6;
|
||||
|
||||
assign w0 = sel[0] ? a[1] : a[0];
|
||||
assign w1 = sel[1] ? a[2] : w0;
|
||||
assign w2 = sel[2] ? w4 : w1;
|
||||
assign w3 = sel[3] ? w2 : w5;
|
||||
assign w4 = sel[2] ? a[3] : w6;
|
||||
assign w5 = sel[5] ? a[5] : w4;
|
||||
assign w6 = w[2] ? a[7] : a[4];
|
||||
assign x = sel[4] ? a[6] : w3;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean and opt_reduce to remove unnecessary cells
|
||||
design -load postopt
|
||||
opt_clean
|
||||
opt_reduce
|
||||
|
||||
# Check we got one pmux with correct number of inputs
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=3 %i
|
||||
select -assert-count 1 t:$pmux r:S_WIDTH=6 %i
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Normal stress test"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [5:0] sel0,
|
||||
input wire [5:0] sel1,
|
||||
input wire [5:0] sel2,
|
||||
input wire [6:0] a0,
|
||||
input wire [6:0] a1,
|
||||
input wire [6:0] a2,
|
||||
output wire x
|
||||
);
|
||||
wire x0, x1;
|
||||
|
||||
// Stage 0
|
||||
wire s0_w0 = sel0[0] ? a0[1] : a0[0];
|
||||
wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
|
||||
wire s0_w2 = sel0[2] ? a0[3] : s0_w1;
|
||||
wire s0_w4 = sel0[5] ? a0[4] : a0[5];
|
||||
wire s0_w3 = sel0[3] ? s0_w2 : s0_w4;
|
||||
assign x0 = sel0[4] ? s0_w3 : a0[6];
|
||||
|
||||
// Stage 1
|
||||
wire s1_w0 = sel1[0] ? a1[1] : a1[0];
|
||||
wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
|
||||
wire s1_w2 = sel1[2] ? a1[3] : s1_w1;
|
||||
wire s1_w4 = sel1[5] ? a1[4] : a1[5];
|
||||
wire s1_w3 = sel1[3] ? s1_w2 : s1_w4;
|
||||
assign x1 = sel1[4] ? s1_w3 : x0;
|
||||
|
||||
// Stage 2
|
||||
wire s2_w0 = sel2[0] ? a2[1] : a2[0];
|
||||
wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
|
||||
wire s2_w2 = sel2[2] ? a2[3] : s2_w1;
|
||||
wire s2_w4 = sel2[5] ? a2[4] : a2[5];
|
||||
wire s2_w3 = sel2[3] ? s2_w2 : s2_w4;
|
||||
assign x = sel2[4] ? s2_w3 : x1;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean and opt_reduce to remove unnecessary cells
|
||||
design -load postopt
|
||||
opt_clean
|
||||
opt_reduce
|
||||
|
||||
# Check we got one pmux with correct number of inputs
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Stress test with reconverging tree and no off chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] sel0,
|
||||
input wire [7:0] sel1,
|
||||
input wire [7:0] sel2,
|
||||
input wire [7:0] a0,
|
||||
input wire [7:0] a1,
|
||||
input wire [7:0] a2,
|
||||
output wire x
|
||||
);
|
||||
wire x0, x1;
|
||||
|
||||
// Stage 0
|
||||
wire s0_w6 = sel0[7] ? a0[7] : a0[4];
|
||||
wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
|
||||
wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
|
||||
wire s0_w0 = sel0[0] ? a0[1] : a0[0];
|
||||
wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
|
||||
wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
|
||||
wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
|
||||
assign x0 = sel0[4] ? a0[6] : s0_w3;
|
||||
|
||||
// Stage 1
|
||||
wire s1_w6 = sel1[7] ? a1[7] : a1[4];
|
||||
wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
|
||||
wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
|
||||
wire s1_w0 = sel1[0] ? a1[1] : x0;
|
||||
wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
|
||||
wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
|
||||
wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
|
||||
assign x1 = sel1[4] ? a1[6] : s1_w3;
|
||||
|
||||
// Stage 2
|
||||
wire s2_w6 = sel2[7] ? a2[7] : a2[4];
|
||||
wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
|
||||
wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
|
||||
wire s2_w0 = sel2[0] ? a2[1] : x1;
|
||||
wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
|
||||
wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
|
||||
wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
|
||||
assign x = sel2[4] ? a2[6] : s2_w3;
|
||||
endmodule
|
||||
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce
|
||||
|
||||
# Load design and run opt_clean and opt_reduce to remove unnecessary cells
|
||||
design -load postopt
|
||||
opt_clean
|
||||
opt_reduce
|
||||
|
||||
# Check we got one pmux with correct number of inputs
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 4 t:$pmux
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Stress test with reconverging tree and yes off chain"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] sel0,
|
||||
input wire [7:0] sel1,
|
||||
input wire [7:0] sel2,
|
||||
input wire [7:0] a0,
|
||||
input wire [7:0] a1,
|
||||
input wire [7:0] a2,
|
||||
output wire x
|
||||
);
|
||||
wire x0, x1;
|
||||
|
||||
// Stage 0
|
||||
wire s0_w6 = sel0[7] ? a0[7] : a0[4];
|
||||
wire s0_w4 = sel0[6] ? a0[3] : s0_w6;
|
||||
wire s0_w5 = sel0[5] ? a0[5] : s0_w4;
|
||||
wire s0_w0 = sel0[0] ? a0[1] : a0[0];
|
||||
wire s0_w1 = sel0[1] ? a0[2] : s0_w0;
|
||||
wire s0_w2 = sel0[2] ? s0_w4 : s0_w1;
|
||||
wire s0_w3 = sel0[3] ? s0_w2 : s0_w5;
|
||||
assign x0 = sel0[4] ? a0[6] : s0_w3;
|
||||
|
||||
// Stage 1
|
||||
wire s1_w6 = sel1[7] ? a1[7] : a1[4];
|
||||
wire s1_w4 = sel1[6] ? a1[3] : s1_w6;
|
||||
wire s1_w5 = sel1[5] ? a1[5] : s1_w4;
|
||||
wire s1_w0 = sel1[0] ? a1[1] : x0;
|
||||
wire s1_w1 = sel1[1] ? a1[2] : s1_w0;
|
||||
wire s1_w2 = sel1[2] ? s1_w4 : s1_w1;
|
||||
wire s1_w3 = sel1[3] ? s1_w2 : s1_w5;
|
||||
assign x1 = sel1[4] ? a1[6] : s1_w3;
|
||||
|
||||
// Stage 2
|
||||
wire s2_w6 = sel2[7] ? a2[7] : a2[4];
|
||||
wire s2_w4 = sel2[6] ? a2[3] : s2_w6;
|
||||
wire s2_w5 = sel2[5] ? a2[5] : s2_w4;
|
||||
wire s2_w0 = sel2[0] ? a2[1] : x1;
|
||||
wire s2_w1 = sel2[1] ? a2[2] : s2_w0;
|
||||
wire s2_w2 = sel2[2] ? s2_w4 : s2_w1;
|
||||
wire s2_w3 = sel2[3] ? s2_w2 : s2_w5;
|
||||
assign x = sel2[4] ? a2[6] : s2_w3;
|
||||
endmodule
|
||||
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after extract_reduce
|
||||
equiv_opt -assert extract_reduce -allow-off-chain
|
||||
|
||||
# Load design and run opt_clean and opt_reduce to remove unnecessary cells
|
||||
design -load postopt
|
||||
opt_clean
|
||||
opt_reduce
|
||||
|
||||
# Check we got one pmux with correct number of inputs
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue