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https://github.com/YosysHQ/yosys.git
synced 2026-08-22 14:17:27 +02:00
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
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@@ -89,8 +89,8 @@ struct EquivSimpleWorker
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bool run_cell()
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{
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SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).to_single_sigbit();
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SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).to_single_sigbit();
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SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
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SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
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int ez_context = ez->frozen_literal();
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if (satgen.model_undef)
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@@ -314,7 +314,7 @@ struct EquivSimplePass : public Pass {
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
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auto bit = sigmap(cell->getPort("\\Y").to_single_sigbit());
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auto bit = sigmap(cell->getPort("\\Y").as_bit());
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auto bit_group = bit;
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if (!nogroup && bit_group.wire)
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bit_group.offset = 0;
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