mirror of https://github.com/YosysHQ/yosys.git
Akash Levy
GitHub
commit
7ea578a212
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@ -11,6 +11,7 @@ OBJS += passes/silimate/obs_clean.o
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OBJS += passes/silimate/segv.o
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OBJS += passes/silimate/reg_rename.o
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OBJS += passes/silimate/infer_ce.o
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OBJS += passes/silimate/ffnormpol.o
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OBJS += passes/silimate/report_fanout.o
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OBJS += passes/silimate/splitfanout.o
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OBJS += passes/silimate/splitlarge.o
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@ -0,0 +1,135 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Silimate Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct FfNormPolPass : public Pass {
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FfNormPolPass() : Pass("ffnormpol", "normalize FF/latch control polarities to positive") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ffnormpol [selection]\n");
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log("\n");
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log("This pass normalizes built-in FF and latch control polarities to\n");
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log("positive polarity. Negative-edge clocks and active-low enables,\n");
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log("resets, sets, clears, and latch enables are rewritten by inserting\n");
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log("inverters on the corresponding control signals and re-emitting the\n");
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log("cell with positive polarity.\n");
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log("\n");
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log("Both coarse-grain cells with polarity parameters and fine-grain cells\n");
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log("with polarity encoded in the cell type are handled through FfData.\n");
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log("\n");
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}
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struct Worker {
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Module *module;
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SigMap sigmap;
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FfInitVals initvals;
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dict<SigSpec, SigSpec> inverted_signals;
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int normalized_cells = 0;
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int normalized_controls = 0;
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Worker(Module *module) : module(module), sigmap(module), initvals(&sigmap, module) { }
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SigSpec invert(SigSpec sig, const char *suffix, const std::string &src)
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{
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sig = sigmap(sig);
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if (inverted_signals.count(sig))
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return inverted_signals.at(sig);
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SigSpec inv = module->Not(NEW_ID_SUFFIX(suffix), sig, false, src);
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inverted_signals[sig] = inv;
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return inv;
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}
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bool normalize(FfData &ff, SigSpec &sig, bool &pol, const char *suffix)
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{
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if (pol)
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return false;
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sig = invert(sig, suffix, ff.attributes[ID::src].decode_string());
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pol = true;
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normalized_controls++;
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return true;
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}
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void run()
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{
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std::vector<Cell *> cells;
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for (auto cell : module->selected_cells())
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if (cell->is_builtin_ff())
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cells.push_back(cell);
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for (auto cell : cells) {
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FfData ff(&initvals, cell);
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bool changed = false;
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if (ff.has_clk)
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changed |= normalize(ff, ff.sig_clk, ff.pol_clk, "ffnormpol_clk");
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if (ff.has_ce)
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changed |= normalize(ff, ff.sig_ce, ff.pol_ce, "ffnormpol_ce");
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if (ff.has_aload)
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changed |= normalize(ff, ff.sig_aload, ff.pol_aload, "ffnormpol_aload");
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if (ff.has_arst)
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changed |= normalize(ff, ff.sig_arst, ff.pol_arst, "ffnormpol_arst");
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if (ff.has_srst)
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changed |= normalize(ff, ff.sig_srst, ff.pol_srst, "ffnormpol_srst");
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if (ff.has_sr) {
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changed |= normalize(ff, ff.sig_clr, ff.pol_clr, "ffnormpol_clr");
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changed |= normalize(ff, ff.sig_set, ff.pol_set, "ffnormpol_set");
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}
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if (changed) {
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ff.emit();
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normalized_cells++;
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}
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}
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}
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};
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing FFNORMPOL pass (normalize FF/latch control polarities).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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break;
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extra_args(args, argidx, design);
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int total_cells = 0;
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int total_controls = 0;
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for (auto module : design->selected_modules()) {
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Worker worker(module);
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worker.run();
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total_cells += worker.normalized_cells;
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total_controls += worker.normalized_controls;
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}
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log("Normalized %d controls on %d FF/latch cells.\n", total_controls, total_cells);
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}
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} FfNormPolPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,116 @@
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log -header "Normalize coarse and fine FF/latch polarities"
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log -push
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design -reset
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read_rtlil <<EOT
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module \top
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wire input 1 \clk
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wire input 2 \en
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wire input 3 \arst
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wire input 4 \srst
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wire input 5 \aload
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wire width 2 input 6 \set
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wire width 2 input 7 \clr
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wire width 2 input 8 \d
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wire width 2 input 9 \ad
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wire width 2 output 10 \q_dffe
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wire width 2 output 11 \q_adffe
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wire width 2 output 12 \q_sdffce
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wire width 2 output 13 \q_aldffe
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wire width 2 output 14 \q_dlatchsr
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wire width 2 output 15 \q_sr
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wire output 16 \q_fine
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cell $dffe \dffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \D \d
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connect \Q \q_dffe
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end
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cell $adffe \adffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \ARST_POLARITY 1'0
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parameter \ARST_VALUE 2'01
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \ARST \arst
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connect \D \d
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connect \Q \q_adffe
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end
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cell $sdffce \sdffce_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \SRST_POLARITY 1'0
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parameter \SRST_VALUE 2'10
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \SRST \srst
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connect \D \d
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connect \Q \q_sdffce
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end
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cell $aldffe \aldffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \ALOAD_POLARITY 1'0
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \ALOAD \aload
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connect \D \d
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connect \AD \ad
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connect \Q \q_aldffe
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end
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cell $dlatchsr \dlatchsr_neg
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parameter \EN_POLARITY 1'0
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parameter \SET_POLARITY 1'0
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parameter \CLR_POLARITY 1'0
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parameter \WIDTH 2
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connect \EN \aload
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connect \SET \set
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connect \CLR \clr
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connect \D \d
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connect \Q \q_dlatchsr
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end
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cell $sr \sr_neg
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parameter \SET_POLARITY 1'0
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parameter \CLR_POLARITY 1'0
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parameter \WIDTH 2
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connect \SET \set
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connect \CLR \clr
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connect \Q \q_sr
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end
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cell $_DFFE_NN_ \fine_dffe_neg
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connect \C \clk
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connect \E \en
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connect \D \d [0]
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connect \Q \q_fine
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end
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end
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EOT
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ffnormpol
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check -assert
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select -assert-count 0 r:CLK_POLARITY=0
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select -assert-count 0 r:EN_POLARITY=0
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select -assert-count 0 r:ARST_POLARITY=0
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select -assert-count 0 r:SRST_POLARITY=0
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select -assert-count 0 r:ALOAD_POLARITY=0
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select -assert-count 0 r:SET_POLARITY=0
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select -assert-count 0 r:CLR_POLARITY=0
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select -assert-count 1 t:$_DFFE_PP_
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select -assert-count 7 t:$not
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design -reset
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log -pop
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