mirror of https://github.com/YosysHQ/yosys.git
commit
7e6f82ad4d
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@ -397,40 +397,11 @@ int FstData::getWidth(fstHandle signal)
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}
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// Auto-discover scope from FST by finding the top module
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std::string FstData::autoScope(Module *topmod) {
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std::string FstData::autoScope(Module *topmod) {
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log("Auto-discovering scope from file...\n");
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log("Auto-discovering scopes from file...\n");
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std::string top = RTLIL::unescape_id(topmod->name);
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log("Available scopes:\n");
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std::set<std::string> unique_scopes;
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for (const auto& var : vars) {
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unique_scopes.insert(var.scope);
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}
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for (const auto& scope : unique_scopes) {
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log(" %s\n", scope.c_str());
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}
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// Option 1 - Instance based scope matching
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// Will fail if the DUT instance name != the top module name
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log("Trying instance-based scope matching...\n");
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for (const auto& var : vars) {
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// Check if this scope ends with our top module
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log_debug("Checking scope: %s\n", var.scope.c_str());
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if (var.scope == top ||
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var.scope.find("." + top) != std::string::npos) {
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// Extract the full path up to (and including) the top module
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size_t pos = var.scope.find(top);
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if (pos != std::string::npos) {
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std::string scope = var.scope.substr(0, pos + top.length());
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return scope;
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}
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}
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}
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// Option 2 - Port based scope matching
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// Matches based on exact port name matching of the top module
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log("Trying port-based scope matching...\n");
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std::string scope = "";
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// Map top module port name to their bit widths (RTL reference point)
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dict<std::string, int> top2widths;
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@ -439,7 +410,7 @@ std::string FstData::autoScope(Module *topmod) {
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top2widths[RTLIL::unescape_id(wire->name)] = wire->width;
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}
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}
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log("Extracted %d ports from top module\n", GetSize(top2widths));
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log("Extracted %d ports from module '%s'\n", GetSize(top2widths), top.c_str());
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// For each scope, track the number of matching ports
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dict<std::string, int> scopes2matches;
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@ -456,7 +427,7 @@ std::string FstData::autoScope(Module *topmod) {
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if (last_dot != std::string::npos) { // no '.' means no scope/signal extraction is possible
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std::string scope = name.substr(0, last_dot);
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std::string signal_name = name.substr(last_dot + 1);
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// Check that signal is in the top module and width matches
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if (top2widths.count(signal_name)) {
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int signal_width = getWidth(handle);
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@ -467,24 +438,28 @@ std::string FstData::autoScope(Module *topmod) {
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}
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}
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// Find scopes with exact matches
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// If there is a tie, return the longest scope
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std::string result = "";
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// Find scopes with exact matches and add to array
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std::vector<std::string> results;
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for (const auto& entry : scopes2matches) {
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int num_matches = entry.second;
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if (num_matches == GetSize(top2widths)) {
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std::string scope = entry.first;
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if (result.empty() || scope.length() > result.length()) {
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result = scope;
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}
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results.push_back(scope);
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}
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}
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if (!result.empty()) {
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return result;
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if (results.empty()) {
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log_warning("Could not auto-discover scope for module '%s'...\n",
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top.c_str());
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return "";
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} else {
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log("Found %d scopes for module '%s':\n", GetSize(results), top.c_str());
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for (const auto& scope : results) {
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log(" %s\n", scope.c_str());
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}
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if (results.size() > 1) {
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log_warning("Multiple scopes found for module '%s'. Using the first one.\n",
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top.c_str());
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}
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return results[0];
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}
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// No match found
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log_warning("Could not auto-discover scope for module '%s'...\n",
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RTLIL::unescape_id(topmod->name).c_str());
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return "";
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}
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