Hell let's add the original #1381 testcase too

tests/techmap/autopurge.ys

@@ -1,4 +1,31 @@
+# https://github.com/YosysHQ/yosys/issues/1381
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
 # https://github.com/YosysHQ/yosys/issues/1391
+design -reset
 read_verilog <<EOT
 module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
 foobar f(i, o, j);
@@ -25,14 +52,6 @@ hierarchy
 check -assert
 
 read_verilog -overwrite <<EOT
-(* blackbox *)
-module sub(input i, output o, input j);
-endmodule
-
-(* blackbox *)
-module foobar(input i, output o, input j);
-endmodule
-
 module top(input i, output o);
 wire j;
 sub s0(i, o, j);