Merge branch 'map_cells_before_map_luts' into xc7srl

techlibs/xilinx/synth_xilinx.cc

@@ -128,6 +128,7 @@ struct SynthXilinxPass : public Pass
 		log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
 		log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
 		log("        clean\n");
+		log("        techmap -map +/xilinx/lut_map.v\n");
 		log("\n");
 		log("    check:\n");
 		log("        hierarchy -check\n");