mirror of https://github.com/YosysHQ/yosys.git
delete redundant .ys files
This commit is contained in:
treelin611
parent
4973d135a2
commit
7a9a01ff8e
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# Yosys synthesis script for ${TOP_MODULE}
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#########################
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# Parse input files
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#########################
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# Read verilog files
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read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
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# Read technology library
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read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
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#########################
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# Prepare for synthesis
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#########################
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# Identify top module from hierarchy
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hierarchy -check -top ${TOP_MODULE}
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# - Convert process blocks to AST
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proc
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# Flatten all the gates/primitives
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flatten
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# Identify tri-state buffers from 'z' signal in AST
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# with follow-up optimizations to clean up AST
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tribuf -logic
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opt_expr
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opt_clean
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# demote inout ports to input or output port
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# with follow-up optimizations to clean up AST
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deminout
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opt -nodffe
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opt_expr
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opt_clean
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check
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opt -nodffe
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wreduce -keepdc
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peepopt
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pmuxtree
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opt_clean
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########################
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# Map multipliers
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# Inspired from synth_xilinx.cc
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#########################
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# Avoid merging any registers into DSP, reserve memory port registers first
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#memory_dff
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#wreduce t:$mul
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#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
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#select a:mul2dsp
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#setattr -unset mul2dsp
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#opt_expr -fine
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#wreduce
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#select -clear
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#chtype -set $mul t:$__soft_mul# Extract arithmetic functions
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#########################
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# Run coarse synthesis
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#########################
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# Run a tech map with default library
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alumacc
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#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
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#opt -fast -nodffe
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#opt_expr
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#opt_merge
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#opt_clean
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#opt -nodffe
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#share
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#opt -nodffe
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#fsm
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# Run a quick follow-up optimization to sweep out unused nets/signals
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#opt -fast -nodffe
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opt
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# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
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memory -nomap
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opt_clean
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#########################
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# Map logics to BRAMs
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#########################
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#memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
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#techmap -map ${YOSYS_BRAM_MAP_VERILOG}
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#opt -fast -mux_undef -undriven -fine -nodffe
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#memory_map
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#opt -undriven -fine -nodffe
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########################
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# Map Adders
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techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
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opt -fast -nodffe
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opt_expr
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opt_merge
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opt_clean
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opt -nodffe
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#########################
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# Map flip-flops
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#########################
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memory
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dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
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techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
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dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
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techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
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opt_expr -mux_undef
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simplemap
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opt_expr
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opt_merge
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opt_dff -nodffe
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opt_clean
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opt -nodffe
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#########################
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# Map LUTs
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#########################
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abc -lut ${LUT_SIZE}
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# Map dff again since ABC may generate some new FFs
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techmap -map ${YOSYS_DFF_MAP_VERILOG}
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techmap -map ${YOSYS_ADDER_MAP_VERILOG}
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#########################
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# Check and show statisitics
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#########################
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hierarchy -check
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stat
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#########################
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# Output netlists
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#########################
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opt_clean -purge
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write_blif ${OUTPUT_BLIF}
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write_verilog ${TOP_MODULE}_post_synth.v
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@ -1,128 +0,0 @@
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# Yosys synthesis script for ${TOP_MODULE}
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#########################
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# Parse input files
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#########################
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# Read verilog files
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read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
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# Read technology library
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read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
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#########################
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# Prepare for synthesis
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#########################
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# Identify top module from hierarchy
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hierarchy -check -top ${TOP_MODULE}
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# - Convert process blocks to AST
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proc
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# Flatten all the gates/primitives
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flatten
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# Identify tri-state buffers from 'z' signal in AST
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# with follow-up optimizations to clean up AST
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tribuf -logic
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opt_expr
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opt_clean
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# demote inout ports to input or output port
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# with follow-up optimizations to clean up AST
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deminout
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opt -nodffe
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opt_expr
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opt_clean
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check
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opt -nodffe
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wreduce -keepdc
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peepopt
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pmuxtree
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opt_clean
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########################
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# Map multipliers
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# Inspired from synth_xilinx.cc
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#########################
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# Avoid merging any registers into DSP, reserve memory port registers first
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#memory_dff
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#wreduce t:$mul
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#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
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#select a:mul2dsp
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#setattr -unset mul2dsp
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#opt_expr -fine
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#wreduce
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#select -clear
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#chtype -set $mul t:$__soft_mul# Extract arithmetic functions
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#########################
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# Run coarse synthesis
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#########################
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# Run a tech map with default library
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alumacc
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#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
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#opt -fast -nodffe
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#opt_expr
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#opt_merge
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#opt_clean
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#opt -nodffe
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#share
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#opt -nodffe
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#fsm
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# Run a quick follow-up optimization to sweep out unused nets/signals
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#opt -fast -nodffe
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opt
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# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
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memory -nomap
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opt_clean
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#########################
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# Map logics to BRAMs
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#########################
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#memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
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#techmap -map ${YOSYS_BRAM_MAP_VERILOG}
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#opt -fast -mux_undef -undriven -fine -nodffe
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#memory_map
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#opt -undriven -fine -nodffe
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########################
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# Map Adders
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#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
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#opt -fast -nodffe
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#opt_expr
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#opt_merge
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#opt_clean
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#opt -nodffe
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#########################
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# Map flip-flops
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#########################
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memory
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dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
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techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
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dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
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techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
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opt_expr -mux_undef
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simplemap
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opt_expr
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opt_merge
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opt_dff -nodffe
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opt_clean
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opt -nodffe
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#########################
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# Map LUTs
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#########################
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abc -lut ${LUT_SIZE}
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# Map dff again since ABC may generate some new FFs
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techmap -map ${YOSYS_DFF_MAP_VERILOG}
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techmap -map ${YOSYS_ADDER_MAP_VERILOG}
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#########################
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# Check and show statisitics
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#########################
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hierarchy -check
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stat
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#########################
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# Output netlists
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#########################
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opt_clean -purge
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write_blif ${OUTPUT_BLIF}
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write_verilog ${TOP_MODULE}_post_synth.v
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@ -1,41 +0,0 @@
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# Yosys synthesis script for ${TOP_MODULE}
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# Read verilog files
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read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
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# Technology mapping
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hierarchy -top ${TOP_MODULE}
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proc
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techmap -D NO_LUT -map +/adff2dff.v
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# Synthesis
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flatten
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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fsm
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opt -nodffe -nosdff
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wreduce
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peepopt
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opt_clean
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opt -nodffe -nosdff
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memory -nomap
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opt_clean
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opt -fast -full -nodffe -nosdff
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memory_map
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opt -full -nodffe -nosdff
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techmap
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opt -fast -nodffe -nosdff
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clean
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clean
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# LUT mapping
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abc -lut ${LUT_SIZE}
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# Check
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synth -run check
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# Clean and output blif
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opt_clean -purge
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write_verilog ${OUTPUT_VERILOG}
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