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synced 2026-08-28 17:14:11 +02:00
rtlil: represent Const strings as std::string
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@@ -97,10 +97,10 @@ struct RomWorker
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log_debug("rejecting switch: lhs not uniform\n");
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return;
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}
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val[it2->second] = it.second[i].data;
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val.bits()[it2->second] = it.second[i].data;
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}
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}
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for (auto bit: val.bits) {
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for (auto bit: val) {
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if (bit == State::Sm) {
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log_debug("rejecting switch: lhs not uniform\n");
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return;
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@@ -113,8 +113,8 @@ struct RomWorker
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return;
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}
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Const c = addr.as_const();
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while (GetSize(c) && c.bits.back() == State::S0)
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c.bits.pop_back();
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while (GetSize(c) && c.back() == State::S0)
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c.bits().pop_back();
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if (GetSize(c) > swsigbits)
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continue;
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if (GetSize(c) > 30) {
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@@ -160,11 +160,11 @@ struct RomWorker
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auto it = vals.find(i);
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if (it == vals.end()) {
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log_assert(got_default);
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for (auto bit: default_val.bits)
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init_data.bits.push_back(bit);
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for (auto bit: default_val)
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init_data.bits().push_back(bit);
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} else {
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for (auto bit: it->second.bits)
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init_data.bits.push_back(bit);
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for (auto bit: it->second)
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init_data.bits().push_back(bit);
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}
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}
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