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opt_mem: Remove constant-value bit lanes.

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This commit is contained in:
Marcelina Kościelnicka
2022-05-07 23:13:16 +02:00
parent 048170d376
commit 77b1dfd8c3
3 changed files with 147 additions and 30 deletions
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tests/techmap/.gitignore
+1
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@@ -1,2 +1,3 @@
*.log
*.out
/*.mk
tests/techmap/mem_simple_4x1_runtest.sh
+1 -15
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@@ -1,17 +1,3 @@
#!/bin/bash
set -e
../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat'
iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v
./mem_simple_4x1_gold_tb > mem_simple_4x1_gold_tb.out
./mem_simple_4x1_gate_tb > mem_simple_4x1_gate_tb.out
diff -u mem_simple_4x1_gold_tb.out mem_simple_4x1_gate_tb.out
rm -f mem_simple_4x1_synth.v mem_simple_4x1_tb.vcd
rm -f mem_simple_4x1_{gold,gate}_tb{,.out}
: OK
exec ../tools/autotest.sh -G -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v