initial import

2026-08-22 14:17:27 +02:00 · 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
481 changed files with 54634 additions and 0 deletions
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+module nonblocking (clk,a,c);
+input clk;
+input a;
+output c;
+ 
+wire clk;
+wire a;
+reg c;
+reg b;
+  
+always @ (posedge clk )
+begin
+  b <= a;
+  c <= b;
+end
+   
+endmodule