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opt_expr: reindent test

This commit is contained in:
Emil J. Tywoniak 2025-12-19 18:30:17 +01:00
parent bd514df0df
commit 772d821fb0
1 changed files with 13 additions and 13 deletions
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26
tests/opt/opt_expr_combined_assign.ys
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@ -5,7 +5,7 @@ initial begin
a |= i; a |= i;
a |= j; a |= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -19,10 +19,10 @@ read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0; wire[8:0] a = 8'b0;
initial begin initial begin
a += i; a += i;
a += j; a += j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -36,10 +36,10 @@ read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0; wire[8:0] a = 8'b0;
initial begin initial begin
a ^= i; a ^= i;
a ^= j; a ^= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -53,10 +53,10 @@ read_verilog -sv <<EOT
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0; wire[8:0] a = 8'b0;
initial begin initial begin
a -= i; a -= i;
a -= j; a -= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -70,10 +70,10 @@ read_verilog -sv <<EOT
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b11111111; wire[8:0] a = 8'b11111111;
initial begin initial begin
a &= i; a &= i;
a &= j; a &= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc